A conventional split-gate flash memory cell is shown in FIG. 1. Two N.sup.+ bit lines 11, 12 are formed as a source 11 and a drain 12 in a p-type silicon substrate 13. A floating gate 14 is formed over part 18b of the channel 18. A drain capacitance is formed between the drain and the floating gate. A control gate 15 is formed over the remainder 18a of the channel 18 and over the floating gate 14. The control gate is separated from the floating gate by an insulating layer or a dielectric 19. A control capacitance is formed between the floating gate and the control gate. The two capacitances form the coupling for driving each cell. The inversion region directly under the control gate is established directly by a "write or read access" voltage applied to the control gate. The inversion region in the channel under the floating gate is indirectly established through the capacitances by the control gate voltage and by another write access voltage applied to the drain. The cell is erased by ultraviolet illumination or by electrons from the floating gate tunneling through a thin oxide 10.
L1 designates the channel length of an isolation transistor and L2 designates the channel length of a floating gate transistor. The floating gate transistor has a source 11, drain 12 and gate 14 and the isolation transistor has a source 11, drain 12 and gate 15. The total channel length is L1+L2 which is defined by a mask. The length L2 of the channel which is beneath the floating gate 14 varies with mask alignment tolerances. Such memory cells are discussed, for example, in U.S. Pat. Nos. 4,868,629 to Eitan and 4,328,565 to Harari, both of which are hereby incorporated by reference.
Flash memories are high-density non-volatile semiconductor memories which offer fast access times. The cell is programmed when charge is stored in the floating gate and unprogrammed when the floating gate is discharged. Generally, the charge is transferred into and out of the floating gate through a thin oxide region. Conventional split-gate transistor cells of the type shown in FIG. 1 do not lend themselves to being reduced in substrate area.
Single transistor flash memory cells are programmed by the application of a positive potential to their drain region and a programming potential to their control gate. This causes the electrons to be transferred onto the floating gate. The cells are erased by a positive potential application to the source region wherein the control gate is grounded and the drain region is left floating. This causes the electrons on the floating gate to tunnel through the gate oxide into the channel and source region. However, single transistor flash memory cell is known to suffer from over-erase problem.
For a flash memory cell, the split-gate structure, as shown in FIG. 1, is known to be able to overcome the over-erase problem but at the expense of a larger cell size. Several publications and patents have been concerned with the fabrication of split-gate structure. For example, U.S. Pat. No. 4,868,629 discloses a structure wherein a photo-resist pattern is used to cover part of the floating gate area and the channel region of the isolation transistor during the process of source/drain N.sup.+ implantation. The isolation transistor is in series with the floating gate transistor. The portion of the transistor channel length under the floating gate will be defined by the floating gate itself. In its preferred embodiment, the drain and source regions are formed by ion implantation and one edge of the floating gate defines the lateral limit of one side of the drain region. A photo-resist extends partially over the floating gate in one direction and beyond the floating gate in the other direction. The source region is defined by an opening in the photo-resist extending beyond the floating gate.
This method is problematic in at least two ways. First, the total channel length, floating gate and isolation gate, cannot easily be consistently controlled because the control is strongly dependent upon the photo-lithography alignment and CD loss. Second, the total channel length, and thus the cell size, tends to be larger due to the same photo lithography process limitation.
U.S. Pat. No. 5,115,288 to Manley, which is hereby incorporated by reference, discloses a method of fabricating an integrated circuit using a conductive spacer to define the gate length of the series select transistor in a split gate memory cell. The length of the spacer can be precisely controlled. A floating gate is formed on a layer of insulating material which covers a substrate. The sides of the floating gate are sealed with insulating material. A conductive spacer is formed adjacent one side of the floating gate and insulated from the floating gate by the seal and from the substrate by the insulating material. The spacer is utilized to defined a self-aligned source and the floating gate is used to define a self-aligned drain. The floating gate only extends over a portion of the channel. The spacer is positioned over the remaining portion of the channel, between the source and the floating gate. A conductive control gate is formed in electrical contact with the spacer. The control gate extends over and is electrically insulated from the floating gate. Therefore, a constant total channel length is produced.
However, this process requires an extra poly layer, that is a three poly process versus a two poly process. Further, one critical photo-masking step, which uses photo-resist, is required to cover half of the floating gate for one-side poly spacer removing. U.S. Pat. No. 4,317,272 to Kuo et al., which is hereby incorporated by reference, discloses an electrically erasable programmable memory cell. An erase window for the first level polysilicon floating gate is positioned beneath a third level poly erase line. Each cell includes a memory transistor (floating gate) Q1, a series enhancement transistor (isolation transistor) Q2 and an erase window C. The series enhancement transistor has a control gate which is an extension of the control gate of the memory transistor without the floating gate interposed. The drains of the Q2 transistors are formed by edges of the inverted channels of the transistors Q1 when Q1 is on. This device is problematic because of its large cell size due to the combined channel length of the two transistors.
Additionally, since two transistors are in series for a split-gate flash cell, a larger cell size than a one-transistor flash cell is inevitable when conventional methods are used to build the cell. The cell size in these conventional memory cells has been large due to the cell layout and configuration. Smaller cell size is desirable in order to provide a more dense array with more cells in a given silicon substrate area and to lower cost and increase manufacture yields.
It is an object of the present invention to provide a process for and structure of a flash memory cell which overcomes the aforementioned problems.